1. Technical Field
The present disclosure relates generally to a semiconductor memory device, and more particularly to a semiconductor memory device having a dummy bit line aligned at an outer area of functional bit lines to provide a photo margin and to maintain pattern uniformity of an adjacent functional bit line.
2. Description of the Related Art
In a semiconductor memory device, a dummy bit line is formed at an outer portion of functional bit lines to ensure a photo margin and to maintain pattern uniformity of the functional bit lines aligned at an outer peripheral portion of a cell region.
The use of dummy bit lines has an advantage in terms of the manufacturing process. However, since the capacitive coupling may occur between a dummy bit line and an adjacent functional bit line, the dummy bit line may exert undesirable influence upon the read sensing operation of the functional bit lines when the adjacent functional bit line is in the floating state, that is, when the adjacent functional bit line is subject to other voltage having the VCC level or the GND level.
In addition, if the dummy bit line is maintained under the predetermined voltage state, the defect may not be detected by applying a test signal from an outside in the inspection stage of the semiconductor memory device. Thus, when a bridge is formed between the dummy bit line and the adjacent functional bit line, the sensing margin of the functional bit line may be weak.